Reduction of power consumption in integrated circuits (IC's) is an ongoing concern in IC development. One way to lower the power consumption of an IC is to reduce the power supply voltage. Reduction of the power supply voltage is generally constrained by the need to meet the circuit's metal oxide semiconductor (MOS) threshold voltage (Vt). Silicon on insulator (SOI) CMOS may be used in place of bulk CMOS as one way to reduce parasitic capacitances and support a lower threshold voltage. Another way to support a lower threshold voltage is to apply a body tie bias from a body contact to a body region, which may be positioned in remote locations from each other in an SOI substrate, with the body tie providing a conductive path between those potentially remote locations.